Nanoelectronics applications will face limits imposed by physics laws, material properties, circuits et systems characteristics, assembly and packaging conditions …
In this context, packaging will play by providing an effective capability of complementing the nanometric device features tio the circuit boards. Interconnecting the nanometric devices will be a major problem, especially on the global level. Assembly approaches are moving toward the system-level integration paradigm and new packaging technologies are proposed (3D system integration, wafer-level packaging, electro/optical integration …) And the conventional materials used in the classical packaging are expected to be inadequate in terms of thermal, mechanical and electrical performances.
A possibility under investigation is the use of new materials in nanopackaging such as carbon nanotubes (CNTs) , nanowires, nanoparticules …Graphene (monoatomic layer of graphite) and/or CNTs (rolled-up sheets of grahene) reveal physical properties, which cannot be encountered in any other materials making them extremely attractive for many applications in the area of nanoelectronics. That explains why the use of CNTs in nanopackaging have to be pushed.
One of the objectives of this project is to study the use of CNTs / graphene for RF applications specially for electrical interconnecting (thermal management will be explore in an other project in parallel with this project). For CNTs / graphene to be effectively deployed as interconnect element, it is important to demonstrate fabrication process with low contact resistance, good direction control and compatibility with CMOS technology. However, fabrication of CNT for all requirements still remains a challenging task.
During this project, the candidate will collaborate with other research fellows to the improvement of the technological process in order to propose innovative connecting elements (CNTs based bumps, graphene based ribbon, …). Such elements will permit both electrical and thermal management with high performances. Experimental test structures will be designed and manufactured in the laboratory. Deembedding techniques will be investigated to fast extract and analyze interconnecting element , and propose circuit models from semiclassical approaches or phenomenological ones. The results will provide a guideline for the future circuit design and fabrication.
Contact: Stéphane Bila